diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 17:40:38 +0300 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 16:10:42 -0600 |
| commit | 7ba28813b41120dd67329fd04dc732ea7fef05a0 (patch) | |
| tree | 6ac134721cc41bbedb8679536b8020b68ebc61b8 /drivers/clk/tegra/clk.h | |
| parent | dd93587be8dc8acf23a0d8a23efc74a91d8f0dfe (diff) | |
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fff520ae72fc..17ddb22f7a50 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -185,6 +185,7 @@ struct tegra_clk_pll_params { * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the * base register. * TEGRA_PLL_BYPASS - PLL has bypass bit + * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring */ struct tegra_clk_pll { struct clk_hw hw; @@ -215,6 +216,7 @@ struct tegra_clk_pll { #define TEGRA_PLLE_CONFIGURE BIT(7) #define TEGRA_PLL_LOCK_MISC BIT(8) #define TEGRA_PLL_BYPASS BIT(9) +#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; |