diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2016-01-14 14:24:37 -0500 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-02-02 15:49:26 +0100 |
| commit | fd2963b071c1346572285a274a6ae8f26a970c4d (patch) | |
| tree | bdc7652551379221c049a13f595ec97db81adff6 /drivers/clk/tegra | |
| parent | f59b0168d3f3257f9bf0734563290acc3c9d972b (diff) | |
clk: tegra: Fix typos around clearing PLLE bits during enable
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d9c3109b75bd..cb28130e6c0a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1401,7 +1401,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val |= PLLE_MISC_IDDQ_SW_CTRL; val &= ~PLLE_MISC_IDDQ_SW_VALUE; val |= PLLE_MISC_PLLE_PTS; - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); pll_writel_misc(val, pll); udelay(5); @@ -2035,7 +2035,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) val |= PLLE_MISC_IDDQ_SW_CTRL; val &= ~PLLE_MISC_IDDQ_SW_VALUE; val |= PLLE_MISC_PLLE_PTS; - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); pll_writel_misc(val, pll); udelay(5); |