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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-04 11:44:20 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-04 11:44:20 -0700
commite4ca4308c055c7bfb82f6756297346760d697953 (patch)
tree886a5a0ab7184e799fdabdf91609bc25a2c12731 /drivers/clk/ti
parente17acfdc83b877794c119fac4627e80510ea3c09 (diff)
parentb11a6face1b6d5518319f797a74e22bb4309daa9 (diff)
Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.17 are mostly additions of new clock drivers and fixes/enhancements to existing clock drivers. There are also some non-critical fixes and improvements to the framework core. Changes to the clock framework core include: - improvements to printks on errors - flattening the previously hierarchal structure of per-clock entries in debugfs - allow per-clock debugfs entries that are specific to a particular clock driver - configure initial clock parent and/or initial clock rate from Device Tree - several feature enhancements to the composite clock type - misc fixes New clock drivers added include: - TI Palmas PMIC - Allwinner A23 SoC - Qualcomm APQ8084 and IPQ8064 SoCs - Rockchip rk3188, rk3066 and rk3288 SoCs - STMicroelectronics STiH407 SoC - Cirrus Logic CLPS711X SoC Many fixes, feature enhancements and further clock tree support for existing clock drivers also were merged, such as Samsung's "ARMCLK down" power saving feature for their Exynos4 & Exynos5 SoCs" * tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: Add missing of_clk_set_defaults export clk: checking wrong variable in __set_clk_parents() clk: Propagate any error return from debug_init() clk: clps711x: Add DT bindings documentation clk: Add CLPS711X clk driver clk: st: Use round to closest divider flag clk: st: Update frequency tables for fs660c32 and fs432c65 clk: st: STiH407: Support for clockgenA9 clk: st: STiH407: Support for clockgenD0/D2/D3 clk: st: STiH407: Support for clockgenC0 clk: st: Add quadfs reset handling clk: st: Add polarity bit indication clk: st: STiH407: Support for clockgenA0 clk: st: STiH407: Support for A9 MUX Clocks clk: st: STiH407: Support for Flexgen Clocks clk: st: Adds Flexgen clock binding clk: st: Remove uncessary (void *) cast clk: st: use static const for clkgen_pll_data tables clk: st: use static const for stm_fs tables clk: st: Update ST clock binding documentation ...
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r--drivers/clk/ti/clk-7xx.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index cb8e6f14e880..62ac8f6e480c 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,6 +18,7 @@
#define DRA7_DPLL_ABE_DEFFREQ 180633600
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+#define DRA7_DPLL_USB_DEFFREQ 960000000
static struct ti_dt_clk dra7xx_clks[] = {
@@ -332,5 +333,15 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+ dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return rc;
}