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authorLinus Walleij <linus.walleij@linaro.org>2013-10-18 10:56:14 +0200
committerLinus Walleij <linus.walleij@linaro.org>2013-10-18 13:25:28 +0200
commitf5ff9a115ec633852312a8e43df4bbd36b4dad3d (patch)
tree585bc178d8f63c33352c22ef155e25d00d56f695 /drivers/clk
parent84873cb77344b9af7c57586c9c144573ebcf0fd1 (diff)
clk: ux500: fix erroneous bit assignment
Due to a typo or similar, the peripheral group 2 clock 11 gate was set to bit 1 instead of bit 11. We need to fix this to be able to set the correct enable bit in the device tree: when trying to correct the bit assignment in the device tree, the system would hang. Cc: Mike Turquette <mturquette@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ux500/u8500_of_clk.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index b768b507c95c..cdeff299de26 100644
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -339,7 +339,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
BIT(11), 0);
- PRCC_PCLK_STORE(clk, 2, 1);
+ PRCC_PCLK_STORE(clk, 2, 11);
clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
BIT(12), 0);