diff options
| author | Abhilash Kesavan <a.kesavan@samsung.com> | 2013-12-12 08:32:00 +0530 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2013-12-30 17:53:26 +0100 |
| commit | 3bf34666a0cce5234ac677ed2fbe5cea82c71329 (patch) | |
| tree | 2b3b3bc1bb14008e43bd9d8de92caa8a690d62b5 /drivers/clk | |
| parent | 97c3557c3e0413efb1f021f582d1459760e22727 (diff) | |
clk: samsung: exynos5250: Fix ACP gate register offset
The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index f862ad8b2b2a..38590237882a 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -25,6 +25,7 @@ #define MPLL_LOCK 0x4000 #define MPLL_CON0 0x4100 #define SRC_CORE1 0x4204 +#define GATE_IP_ACP 0x8800 #define CPLL_LOCK 0x10020 #define EPLL_LOCK 0x10030 #define VPLL_LOCK 0x10040 @@ -75,7 +76,6 @@ #define SRC_CDREX 0x20200 #define PLL_DIV2_SEL 0x20a24 #define GATE_IP_DISP1 0x10928 -#define GATE_IP_ACP 0x10000 /* list of PLLs to be registered */ enum exynos5250_plls { |