diff options
| author | Guoniu.Zhou <guoniu.zhou@nxp.com> | 2018-05-28 11:03:56 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:59 +0800 |
| commit | 0d51ef1acddbc1406273c151fe96ec4113b3639b (patch) | |
| tree | 2f702db4ab2b9835cb797e7451cba23e9166eb11 /drivers/clk | |
| parent | 9556b5d9fcf2ff1e855a0d9b86c2f023ae9701aa (diff) | |
MLK-18407: clk: accommodate scfw change for QXP PI ss
Change pixel clock register of qxp PI ss in order to
accommodate scfw change for PI ss
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 1a769a426f4dcbd145280b3ff613607fbf6bcaa4)
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 3ed7d9d6d200..6e7e1f5b1275 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -564,8 +564,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX8QXP_PARALLEL_CSI_CLK_SEL] = imx_clk_mux2_scu("pll0_sel", pll0_sels, ARRAY_SIZE(pll0_sels), SC_R_PI_0, SC_PM_CLK_PER); clks[IMX8QXP_PARALLEL_CSI_PER_CLK_DIV] = imx_clk_divider2_scu("parallel_per_clk", "pll0_sel", SC_R_PI_0, SC_PM_CLK_PER); clks[IMX8QXP_PARALLEL_CSI_MCLK_DIV] = imx_clk_divider_scu("parallel_csi_mclk_div", SC_R_PI_0, SC_PM_CLK_MISC0); - clks[IMX8QXP_PARALLEL_CSI_PIXEL_CLK] = imx_clk_gate2_scu("parallel_pixel_clk", "parallel_per_clk", (void __iomem *)(PARALLEL_CSI_LPCG + 0x18), 0, FUNCTION_NAME(PD_PARALLEL_CSI)); - clks[IMX8QXP_PARALLEL_CSI_IPG_CLK] = imx_clk_gate2_scu("parallel_ipg_clk", "parallel_per_clk", (void __iomem *)(PARALLEL_CSI_LPCG + 0x4), 16, FUNCTION_NAME(PD_PARALLEL_CSI)); + clks[IMX8QXP_PARALLEL_CSI_PIXEL_CLK] = imx_clk_gate_scu("parallel_pixel_clk", "parallel_per_clk", SC_R_PI_0, SC_PM_CLK_PER, (void __iomem *)(PARALLEL_CSI_LPCG + 0x18), 0, 0); + clks[IMX8QXP_PARALLEL_CSI_IPG_CLK] = imx_clk_gate_scu("parallel_ipg_clk", "parallel_per_clk", SC_R_PI_0, SC_PM_CLK_PER, (void __iomem *)(PARALLEL_CSI_LPCG + 0x4), 16, 0); clks[IMX8QXP_PARALLEL_CSI_MISC0_CLK] = imx_clk_gate_scu("parallel_csi_mclk", "parallel_csi_mclk_div", SC_R_PI_0, SC_PM_CLK_MISC0, (void __iomem *)(PARALLEL_CSI_LPCG + 0x1C), 0, 0); |