diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2017-09-07 23:12:40 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:35 +0800 |
| commit | e3a6b93c107bcce86be56c9bffea337b7e0c3a0d (patch) | |
| tree | 6b501d35561f406375cc4b538fc4582287faf35c /drivers/clk | |
| parent | 828d147c18a9a226d87859979f1da6c20e55b0e4 (diff) | |
MLK-17491-46 clk: imx7ulp: add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx7ulp.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 4f7b84eb4312..8b906e1a2bdd 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -119,6 +119,9 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node) clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels)); clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_mux("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels)); + clks[IMX7ULP_CLK_SPLL_BUS_CLK] = clk_register_divider_table(NULL, "spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, + CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ZERO_GATE, ulp_div_table, &imx_ccm_lock); + /* sys/ddr/nic select different clock source requires that clock to be enabled first */ clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_mux2("sys_sel", base + 0x14, 24, 4, sys_sels, ARRAY_SIZE(sys_sels)); clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_mux2("hsrun_sys_sel", base + 0x1c, 24, 4, sys_sels, ARRAY_SIZE(sys_sels)); @@ -141,6 +144,11 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node) clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_divider("gpu_div", "nic0_div", base + 0x40, 20, 4); + clks[IMX7ULP_CLK_SOSC_BUS_CLK] = clk_register_divider_table(NULL, "sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3, + CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ZERO_GATE, ulp_div_table, &imx_ccm_lock); + clks[IMX7ULP_CLK_FIRC_BUS_CLK] = clk_register_divider_table(NULL, "firc_bus_clk", "firc", 0, base + 0x304, 8, 3, + CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ZERO_GATE, ulp_div_table, &imx_ccm_lock); + /* PCC2 */ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2"); base = of_iomap(np, 0); |