diff options
| author | Yuchou Gan <yuchou.gan@nxp.com> | 2018-03-31 01:45:52 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:08 +0800 |
| commit | f70502b266b56191baaf05772bdd85ce10364d18 (patch) | |
| tree | a42895d0e714057fe9b01a6b08c481d1f8aceb3d /drivers/clk | |
| parent | 28363e4c22dee0c95ecd06eb531bf635b3f977a3 (diff) | |
MGS-3786 [#ccc] Cncrease the clock rate of GPU3D/GPU2D for 7ulp B0 board
The gpu3d/2d clock rate for 7ulp B0 board is 400M, increase it
Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx7ulp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index a2853b5acd64..6eb9b8ffbfb4 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -208,7 +208,7 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node) imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]); imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]); - imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000); + imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 400000000); /* setting the rate for emmc/sd usage */ imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD1], 352800000); |