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authorRobert Yang <decatf@gmail.com>2018-09-25 17:49:40 -0400
committerStephen Boyd <sboyd@kernel.org>2018-12-14 13:32:55 -0800
commit08441a966219aee513cf802ca8de170c6655c61a (patch)
treee7049b99c5eb948d2535fad72aec7bdbed323737 /drivers/clk
parentb158aeeacc551a689dc26824800a0a27f3668bb1 (diff)
clk: tegra: Return the exact clock rate from clk_round_rate
The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API. Signed-off-by: Robert Yang <decatf@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-pll.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 830d1c87fa7c..b50b7460014b 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -590,12 +590,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
- if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
- (1 << p_div) > divp_max(pll)
- || cfg->output_rate > pll->params->vco_max) {
+ if (cfg->m == 0 || cfg->m > divm_max(pll) ||
+ cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
+ cfg->output_rate > pll->params->vco_max) {
return -EINVAL;
}
+ cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
cfg->output_rate >>= p_div;
if (pll->params->pdiv_tohw) {