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authorMark Langsdorf <mark.langsdorf@calxeda.com>2013-01-28 16:13:13 +0000
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-02-02 00:01:15 +0100
commitb5964708532f4713e9cfb1b8b1a6ac8544fc66af (patch)
treeac0b962debf44ef6a15a6ea0a652633f1afe372f /drivers/clk
parentbd603455f366bd66a5e1870bc285c05c9cb6a72d (diff)
clk / highbank: Prevent glitches in non-bypass reset mode
The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-highbank.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 52fecadf004a..3a0b723da2bc 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
reg |= HB_PLL_EXT_ENA;
reg &= ~HB_PLL_EXT_BYPASS;
} else {
+ writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
reg &= ~HB_PLL_DIVQ_MASK;
reg |= divq << HB_PLL_DIVQ_SHIFT;
+ writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
}
writel(reg, hbclk->reg);