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authorDan Carpenter <dan.carpenter@oracle.com>2015-05-14 13:05:00 +0300
committerYoshinori Sato <ysato@users.sourceforge.jp>2015-06-23 13:35:58 +0900
commitded515a4d5561bc930de4e42a8621b1edd481f22 (patch)
treefceaf8065900406433039ebf32f06190cc32bb39 /drivers/clk
parent389456b74007c6f455bec9d11e6c7cfc64d6e8d0 (diff)
clk: h8300: fix error handling in h8s2678_pll_clk_setup()
The error handling was a bit messy and buggy. It freed "pll_clock" then dereferenced it, and then freed it again. I've re-written it in normal kernel style. Fixes: 42ff8e8008c8 ('h8300: clock driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/h8300/clk-h8s2678.c33
1 files changed, 16 insertions, 17 deletions
diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c
index 4de7ee534bfc..4701b093e497 100644
--- a/drivers/clk/h8300/clk-h8s2678.c
+++ b/drivers/clk/h8300/clk-h8s2678.c
@@ -107,13 +107,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
pll_clock->sckcr = of_iomap(node, 0);
if (pll_clock->sckcr == NULL) {
pr_err("%s: failed to map divide register", clk_name);
- goto error;
+ goto free_clock;
}
pll_clock->pllcr = of_iomap(node, 1);
if (pll_clock->pllcr == NULL) {
pr_err("%s: failed to map multiply register", clk_name);
- goto error;
+ goto unmap_sckcr;
}
parent_name = of_clk_get_parent_name(node, 0);
@@ -125,22 +125,21 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
pll_clock->hw.init = &init;
clk = clk_register(NULL, &pll_clock->hw);
- if (IS_ERR(clk))
- kfree(pll_clock);
- if (!IS_ERR(clk)) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- return;
- }
- pr_err("%s: failed to register %s div clock (%ld)\n",
- __func__, clk_name, PTR_ERR(clk));
-error:
- if (pll_clock) {
- if (pll_clock->sckcr)
- iounmap(pll_clock->sckcr);
- if (pll_clock->pllcr)
- iounmap(pll_clock->pllcr);
- kfree(pll_clock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register %s div clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ goto unmap_pllcr;
}
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+unmap_pllcr:
+ iounmap(pll_clock->pllcr);
+unmap_sckcr:
+ iounmap(pll_clock->sckcr);
+free_clock:
+ kfree(pll_clock);
}
CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",