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author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 17:38:28 +0100 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-22 00:29:23 +0200 |
commit | 7f2ea3847d47d49929d41573a3b26c80ddebbef5 (patch) | |
tree | f7a4ab1eadcea14597f1f2ad9bd8cb8bbda6f4a0 /drivers/clk | |
parent | f4b9ef653c047165f096d32816904be5ee337a63 (diff) |
dt-bindings: clk: sun5i: add DRAM gates compatible
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk')
0 files changed, 0 insertions, 0 deletions