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authorLoc Ho <lho@apm.com>2016-02-29 14:15:43 -0700
committerStephen Boyd <sboyd@codeaurora.org>2016-03-03 11:37:15 -0800
commit0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 (patch)
treeb4475ae1c48153863410752a359ed4a13df3a0c3 /drivers/clk
parent0d9967fe4ba6fc3a57d946a54bcba2d0b3ef8e0b (diff)
clk: xgene: Add missing parenthesis when clearing divider value
In the initial fix for non-zero divider shift value, the parenthesis was missing after the negate operation. This patch adds the required parenthesis. Otherwise, lower bits may be cleared unintentionally. Signed-off-by: Loc Ho <lho@apm.com> Acked-by: Toan Le <toanle@apm.com> Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-xgene.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index bd7156baa08b..d73450b60b28 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -376,8 +376,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
/* Set new divider */
data = xgene_clk_read(pclk->param.divider_reg +
pclk->param.reg_divider_offset);
- data &= ~((1 << pclk->param.reg_divider_width) - 1)
- << pclk->param.reg_divider_shift;
+ data &= ~(((1 << pclk->param.reg_divider_width) - 1)
+ << pclk->param.reg_divider_shift);
data |= divider;
xgene_clk_write(data, pclk->param.divider_reg +
pclk->param.reg_divider_offset);