diff options
| author | Victoria Milhoan (b42089) <vicki.milhoan@freescale.com> | 2013-03-26 14:11:32 -0700 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-20 14:28:44 -0600 |
| commit | 5e42172dcbda4be044f092e5943f5c3f94163ffa (patch) | |
| tree | 83c5b4739f56056ac1850dfba7a192d24b6dbd3f /drivers/crypto/caam | |
| parent | bd29b62c10c3dbcd33da90b9e435b613fa5151e1 (diff) | |
MLK-9769-20 Limit AXI pipeline to a depth of one in CAAM for i.MX6 devices
i.MX6 devices have an issue wherein AXI bus transactions may not occur
in the correct order. This isn't a problem running single descriptors,
but can be if running multiple concurrent descriptors. Reworking the CAAM
driver to throttle to single requests is impractical, so this patch limits
the AXI pipeline to a depth of one (from a default of four) to preclude
this situation from occurring.
Signed-off-by: Victoria Milhoan (b42089) <vicki.milhoan@freescale.com>
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
Diffstat (limited to 'drivers/crypto/caam')
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 7edd46c516d5..5d71b53d2736 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -544,6 +544,21 @@ static int caam_probe(struct platform_device *pdev) setbits32(&ctrl->mcr, MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); +#ifdef CONFIG_ARCH_MX6 + /* + * ERRATA: mx6 devices have an issue wherein AXI bus transactions + * may not occur in the correct order. This isn't a problem running + * single descriptors, but can be if running multiple concurrent + * descriptors. Reworking the driver to throttle to single requests + * is impractical, thus the workaround is to limit the AXI pipeline + * to a depth of 1 (from it's default of 4) to preclude this situation + * from occurring. + */ + wr_reg32(&topregs->ctrl.mcr, + (rd_reg32(&topregs->ctrl.mcr) & ~(MCFGR_AXIPIPE_MASK)) | + ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK)); +#endif + /* * Read the Compile Time paramters and SCFGR to determine * if Virtualization is enabled for this platform @@ -570,6 +585,7 @@ static int caam_probe(struct platform_device *pdev) JRSTART_JR1_START | JRSTART_JR2_START | JRSTART_JR3_START); + /* Set DMA masks according to platform ranging */ if (sizeof(dma_addr_t) == sizeof(u64)) if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); |