diff options
| author | ye li <ye.li@nxp.com> | 2016-09-09 22:06:57 +0800 |
|---|---|---|
| committer | ye li <ye.li@nxp.com> | 2016-09-12 19:42:53 +0800 |
| commit | d3aac3f5b0d2e0dd0fa1e8b165d465f4e4b7d979 (patch) | |
| tree | d95fbe6626fd0852799f7efa4d584860639aef8e /drivers/crypto | |
| parent | 15c88df94f6c70ba77e979db1a7e9a467fbce578 (diff) | |
MLK-12997 CRYPTO: CAAM: Fix kernel hang in CAAM when HAB boot
When HAB boot, the CAAM clocks are disabled after authenticate kernel image.
But the CAAM driver accesses the CTPR_MS register earlier than enabling clocks,
which causes kernel hang.
Fix the issue by moving the page size getting later than clocks enabling.
Signed-off-by: ye li <ye.li@nxp.com>
(cherry picked from commit 781ffdb82e9a08521394e6a3b94a4354e94c51eb)
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 43 |
1 files changed, 22 insertions, 21 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index c81167442197..c160f83ae6a0 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -468,27 +468,6 @@ static int caam_probe(struct platform_device *pdev) dev_err(dev, "caam: of_iomap() failed\n"); return -ENOMEM; } - /* Finding the page size for using the CTPR_MS register */ - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); - pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; - - /* Allocating the BLOCK_OFFSET based on the supported page size on - * the platform - */ - if (pg_size == 0) - BLOCK_OFFSET = PG_SIZE_4K; - else - BLOCK_OFFSET = PG_SIZE_64K; - - ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; - ctrlpriv->assure = (struct caam_assurance __force *) - ((uint8_t *)ctrl + - BLOCK_OFFSET * ASSURE_BLOCK_NUMBER - ); - ctrlpriv->deco = (struct caam_deco __force *) - ((uint8_t *)ctrl + - BLOCK_OFFSET * DECO_BLOCK_NUMBER - ); /* Get CAAM-SM node and of_iomap() and save */ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); @@ -584,6 +563,28 @@ static int caam_probe(struct platform_device *pdev) } #endif + /* Finding the page size for using the CTPR_MS register */ + comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); + pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; + + /* Allocating the BLOCK_OFFSET based on the supported page size on + * the platform + */ + if (pg_size == 0) + BLOCK_OFFSET = PG_SIZE_4K; + else + BLOCK_OFFSET = PG_SIZE_64K; + + ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; + ctrlpriv->assure = (struct caam_assurance __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * ASSURE_BLOCK_NUMBER + ); + ctrlpriv->deco = (struct caam_deco __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * DECO_BLOCK_NUMBER + ); + /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register |