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authorLaxman Dewangan <ldewangan@nvidia.com>2011-07-15 14:36:16 +0530
committerVarun Colbert <vcolbert@nvidia.com>2011-07-18 17:42:44 -0700
commitbbbb88d21d166eeb4de4d83af073f08bdcbe1257 (patch)
tree55848673afb311114291095c74a97ee3664c092d /drivers/crypto
parent3f524b73df7fe3860ae532692b55e40274ddc043 (diff)
arm: tegra: cardhu: Set AVDD_PLL and AVDD_PLL_SATA to proper voltage
Setting the rail voltage of the AVDD_PLLs to 1.2V and rail voltage of PLL_SATA to 1.05V. Change-Id: Ibf5bb1d11b7b15cabb68f90da7e24dd999915c55 Reviewed-on: http://git-master/r/41179 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers/crypto')
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