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author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-03-18 14:26:32 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-05-04 14:48:42 -0700 |
commit | 34c1b030296c6815c05e416c7a647b68e695004a (patch) | |
tree | 7aab4a428650a9b3ccb3360090aadfa90f5acab2 /drivers/dma/imx-sdma.c | |
parent | 42e6f01a44fe4aab28819b5efa48fbe9da3059e5 (diff) |
dmaengine: hsu: correct use of channel status register
commit 4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab upstream.
There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.
Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.
Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.
Fixes: 2b49e0c56741 ("dmaengine: append hsu DMA driver")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/dma/imx-sdma.c')
0 files changed, 0 insertions, 0 deletions