diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-04-13 18:10:14 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:36:16 +0800 |
| commit | 78b315e4615ab22ea2a20eb516253fc3ebf9fadb (patch) | |
| tree | 057af23690d75f1e1ad6a04519f7ff70fad8fa6f /drivers/dma | |
| parent | ad56c8ebc569fc9cc79b5cda78dab15418efd1d8 (diff) | |
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers/dma')
0 files changed, 0 insertions, 0 deletions