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authorHan Xu <han.xu@nxp.com>2017-11-10 17:37:22 -0600
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commit4f5b0b05cdc7eb9ea091c50ffc9fc162ee1c5e21 (patch)
treee3b63a7302c360020e6692a4e8d5bcdf6f56b99a /drivers/dma
parent4da9e27b319b8a514eb6bc541e368073dc74f584 (diff)
MLK-16800: dma: mxs-dma: correctly handle mxs-dma clock
enable mxs-dma clock before HW reset and disable clock after it. BuildInfo: - SCFW 15d20cde, IMX-MKIMAGE ff9860c5, ATF - U-Boot 2017.03-00003-gd09f5db Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/mxs-dma.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index f585b2737c9a..1b829d59d2a1 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -1,5 +1,6 @@
/*
* Copyright 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2017 NXP
*
* Refer to drivers/dma/imx-sdma.c
*
@@ -728,12 +729,19 @@ static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma)
static int mxs_dma_init(struct mxs_dma_engine *mxs_dma)
{
+ struct device *dev = &mxs_dma->pdev->dev;
int ret;
ret = mxs_dma_init_rpm(mxs_dma);
if (ret)
return ret;
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable clock\n");
+ return ret;
+ }
+
ret = stmp_reset_block(mxs_dma->base);
if (ret)
goto err_clk;
@@ -750,6 +758,9 @@ static int mxs_dma_init(struct mxs_dma_engine *mxs_dma)
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
err_clk:
return ret;
}