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authorVinod Koul <vinod.koul@intel.com>2013-06-12 13:39:57 +0530
committerVinod Koul <vinod.koul@intel.com>2013-07-05 11:40:46 +0530
commite368b510c01aaf7b2957306836ffdeacc24712a3 (patch)
tree634a8da8326eae909bbf66fd256c1e71ff74a3f5 /drivers/dma
parentfed42c198b45ece0b37eb25d37cbc4a9959c6522 (diff)
dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/dw/Kconfig11
-rw-r--r--drivers/dma/dw/regs.h6
2 files changed, 8 insertions, 9 deletions
diff --git a/drivers/dma/dw/Kconfig b/drivers/dma/dw/Kconfig
index db2b41fab626..dde13248b681 100644
--- a/drivers/dma/dw/Kconfig
+++ b/drivers/dma/dw/Kconfig
@@ -10,6 +10,7 @@ config DW_DMAC_CORE
config DW_DMAC
tristate "Synopsys DesignWare AHB DMA platform driver"
select DW_DMAC_CORE
+ select DW_DMAC_BIG_ENDIAN_IO if AVR32
default y if CPU_AT32AP7000
help
Support the Synopsys DesignWare AHB DMA controller. This
@@ -25,12 +26,4 @@ config DW_DMAC_PCI
Intel Medfield has integrated this GPDMA controller.
config DW_DMAC_BIG_ENDIAN_IO
- bool "Use big endian I/O register access"
- default y if AVR32
- depends on DW_DMAC_CORE
- help
- Say yes here to use big endian I/O access when reading and writing
- to the DMA controller registers. This is needed on some platforms,
- like the Atmel AVR32 architecture.
-
- If unsure, use the default setting.
+ bool
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 07c5a6ecb52b..deb4274f80f4 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -101,6 +101,12 @@ struct dw_dma_regs {
u32 DW_PARAMS;
};
+/*
+ * Big endian I/O access when reading and writing to the DMA controller
+ * registers. This is needed on some platforms, like the Atmel AVR32
+ * architecture.
+ */
+
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
#define dma_readl_native ioread32be
#define dma_writel_native iowrite32be