diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2020-05-05 14:32:33 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-30 00:59:49 -0400 |
| commit | e0457659f8d842908510fb485c32cb4da829900d (patch) | |
| tree | e945f2898a57132c684420fe4b8d31f32d45e45c /drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | |
| parent | d95c368ab8cf969a41ca7594a77c5c38d22a926d (diff) | |
drm/amd/display: allow 18 bit dp output on DCN3
We need this to pass dp compliance.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nikola Cornij <nikola.cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index d1ed2a99bf65..d65496917e93 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw( dml_log_mode_support_params(&context->bw_ctx.dml); - /* TODO: Need to check calculated vlevel why that fails validation of below resolutions */ - if (context->res_ctx.pipe_ctx[0].stream != NULL) { - if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480) - vlevel = 0; - if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800) - vlevel = 0; - if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768) - vlevel = 0; - if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024) - vlevel = 0; - if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536) - vlevel = 0; - } - if (vlevel == context->bw_ctx.dml.soc.num_states) goto validate_fail; |