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| author | Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> | 2023-06-01 13:45:05 +0300 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-06-19 15:31:12 +0200 |
| commit | 2a787aca993b5c502a3d7cdae85e0ddce826788d (patch) | |
| tree | aaf455942b242235c631a496700f3c6f4c7569d1 /drivers/gpu/drm/bridge/lontium-lt8912b.c | |
| parent | e6d358de2348661f5cd06f2ce6bc3d39d42e95ef (diff) | |
HACK: drm: tidss: clk_set_rate issue workaround
Sometimes when changing the VP clock rate, the result is getting a clock
rate of 0, which obviously then breaks the display. As a quick
workaround, setting the rate a second time seems to fix the problem.
Upstream-Status: Inappropriate [other]
Just a temporary hack, this should be fixed on the TI SYSFW.
Reported to TI [1] and waiting for a fix.
[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1239552/am625-clk_set_rate-failing-on-tidss-driver-sysfw-bug
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Diffstat (limited to 'drivers/gpu/drm/bridge/lontium-lt8912b.c')
0 files changed, 0 insertions, 0 deletions