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authorTomi Valkeinen <tomi.valkeinen@ti.com>2019-05-28 11:27:35 +0300
committerAndrzej Hajda <a.hajda@samsung.com>2019-05-31 15:41:23 +0200
commit67bca92fa83089e7091e7210777b2f9ea17e5f87 (patch)
treeb90293487b0ff5cb4350d11db3d131070e247443 /drivers/gpu/drm/bridge
parent1c928267b187a59ce96972a3102acb9ba72890e1 (diff)
drm/bridge: tc358767: ensure DP is disabled before LT
Link training will sometimes fail if the DP link is enabled when tc_main_link_enable() is called. The driver makes sure the DP link is disabled when the DP output is disabled, and we never enable the DP without first disabling it, so this should never happen. However, as the HW behavior seems to be somewhat random if DP link has erroneously been left enabled, let's add a WARN_ON() for the case and set DP0CTL to 0. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528082747.3631-13-tomi.valkeinen@ti.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
-rw-r--r--drivers/gpu/drm/bridge/tc358767.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index f004db06dee9..ccf4c8cfbb52 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -839,6 +839,10 @@ static int tc_main_link_enable(struct tc_data *tc)
dev_dbg(tc->dev, "link enable\n");
+ tc_read(DP0CTL, &value);
+ if (WARN_ON(value & DP_EN))
+ tc_write(DP0CTL, 0);
+
tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
tc_write(DP1_SRCCTRL,