diff options
| author | Jean-Francois Moine <moinejf@free.fr> | 2014-01-25 18:14:42 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-02-13 19:41:48 +0000 |
| commit | 81b53a166f5cdf4e5bec47fc8884c994de82dc6b (patch) | |
| tree | e368105a435205e09107e7830912c9a0643bfa66 /drivers/gpu/drm/i2c | |
| parent | 73d5e253ac641bf95f5836c064128be78f43cd0b (diff) | |
drm/i2c: tda998x: don't read write-only registers
This patch takes care of the write-only registers of the tda998x.
The registers SOFTRESET, TBG_CNTRL_0 and TBG_CNTRL_1 have all bits
cleared after reset, so, they may be fully re-written.
The register MAT_CONTRL is set to
MAT_CONTRL_MAT_BP | MAT_CONTRL_MAT_SC(1)
after reset, so, it may be fully set again to this value.
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/gpu/drm/i2c')
| -rw-r--r-- | drivers/gpu/drm/i2c/tda998x_drv.c | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index 80b94b51e060..d31e1c170bb6 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -496,9 +496,9 @@ static void tda998x_reset(struct tda998x_priv *priv) { /* reset audio and i2c master: */ - reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); + reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); msleep(50); - reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); + reg_write(priv, REG_SOFTRESET, 0); msleep(50); /* reset transmitter: */ @@ -860,7 +860,7 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); /* set HDMI HDCP mode off: */ - reg_set(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); + reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); reg_clear(priv, REG_TX33, TX33_HDMI); reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); @@ -887,38 +887,28 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, PLL_SERIAL_2_SRL_PR(rep)); /* set color matrix bypass flag: */ - reg_set(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); + reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | + MAT_CONTRL_MAT_SC(1)); /* set BIAS tmds value: */ reg_write(priv, REG_ANA_GENERAL, 0x09); - reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); + reg_write(priv, REG_TBG_CNTRL_0, 0); /* * Sync on rising HSYNC/VSYNC */ - reg_write(priv, REG_VIP_CNTRL_3, 0); - reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); + reg = VIP_CNTRL_3_SYNC_HS; /* * TDA19988 requires high-active sync at input stage, * so invert low-active sync provided by master encoder here */ if (mode->flags & DRM_MODE_FLAG_NHSYNC) - reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); + reg |= VIP_CNTRL_3_H_TGL; if (mode->flags & DRM_MODE_FLAG_NVSYNC) - reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); - - /* - * Always generate sync polarity relative to input sync and - * revert input stage toggled sync at output stage - */ - reg = TBG_CNTRL_1_TGL_EN; - if (mode->flags & DRM_MODE_FLAG_NHSYNC) - reg |= TBG_CNTRL_1_H_TGL; - if (mode->flags & DRM_MODE_FLAG_NVSYNC) - reg |= TBG_CNTRL_1_V_TGL; - reg_write(priv, REG_TBG_CNTRL_1, reg); + reg |= VIP_CNTRL_3_V_TGL; + reg_write(priv, REG_VIP_CNTRL_3, reg); reg_write(priv, REG_VIDFORMAT, 0x00); reg_write16(priv, REG_REFPIX_MSB, ref_pix); @@ -947,13 +937,25 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, reg_write(priv, REG_ENABLE_SPACE, 0x00); } + /* + * Always generate sync polarity relative to input sync and + * revert input stage toggled sync at output stage + */ + reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + reg |= TBG_CNTRL_1_H_TGL; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + reg |= TBG_CNTRL_1_V_TGL; + reg_write(priv, REG_TBG_CNTRL_1, reg); + /* must be last register set: */ - reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); + reg_write(priv, REG_TBG_CNTRL_0, 0); /* Only setup the info frames if the sink is HDMI */ if (priv->is_hdmi_sink) { /* We need to turn HDMI HDCP stuff on to get audio through */ - reg_clear(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); + reg &= ~TBG_CNTRL_1_DWIN_DIS; + reg_write(priv, REG_TBG_CNTRL_1, reg); reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); reg_set(priv, REG_TX33, TX33_HDMI); |