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author | Stefan Agner <stefan.agner@toradex.com> | 2019-11-12 13:57:30 +0100 |
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committer | Stefan Agner <stefan.agner@toradex.com> | 2019-11-12 13:57:30 +0100 |
commit | 401bf3f29b1aa6d9ca32bd3252fc9beabe93d80b (patch) | |
tree | 6dd86325823a9b44b6e696acbd077e68c47d3108 /drivers/gpu/drm/i915/display/intel_dpll_mgr.c | |
parent | 5a9c845fe261dec87f892f3fd3c2e32604d952c0 (diff) | |
parent | b260a0862e3a9fccdac23ec3b783911b098c1c74 (diff) |
Merge tag 'v5.3.10' into toradex_5.3.ytoradex_5.3.y
This is the 5.3.10 stable release
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 2d4e7b9a7b9d..f199a6769962 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -498,16 +498,31 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, val = I915_READ(WRPLL_CTL(id)); I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); POSTING_READ(WRPLL_CTL(id)); + + /* + * Try to set up the PCH reference clock once all DPLLs + * that depend on it have been shut down. + */ + if (dev_priv->pch_ssc_use & BIT(id)) + intel_init_pch_refclk(dev_priv); } static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { + enum intel_dpll_id id = pll->info->id; u32 val; val = I915_READ(SPLL_CTL); I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); POSTING_READ(SPLL_CTL); + + /* + * Try to set up the PCH reference clock once all DPLLs + * that depend on it have been shut down. + */ + if (dev_priv->pch_ssc_use & BIT(id)) + intel_init_pch_refclk(dev_priv); } static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, |