diff options
| author | Imre Deak <imre.deak@intel.com> | 2013-04-17 14:04:50 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-10 21:56:35 +0200 |
| commit | 7d708ee40a6b9ca1112a322e554c887df105b025 (patch) | |
| tree | ce5a29a139c6e6c1c0c2d3e156ba3f8f48800baf /drivers/gpu/drm/i915/i915_drv.c | |
| parent | bc5ead8c09b51e85d110132495a9bfa58dc39dab (diff) | |
drm/i915: HSW: allow PCH clock gating for suspend
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 40b57871a0bf..707a56ec389d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -529,6 +529,8 @@ static int i915_drm_freeze(struct drm_device *dev) */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) dev_priv->display.crtc_disable(crtc); + + intel_modeset_suspend_hw(dev); } i915_save_state(dev); |