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authorEric Anholt <eric@anholt.net>2010-03-08 23:41:55 -0800
committerEric Anholt <eric@anholt.net>2010-03-17 12:59:32 -0700
commit71cf39b117d5aa817a4693f4478397e6b04bee25 (patch)
tree7c7dd6fb84629e4fbc7b4c70f1b55889bcf0d200 /drivers/gpu/drm/i915/i915_gem.c
parent4967790112b284f276c5065dc724f7340a2fd7a5 (diff)
drm/i915: Enable VS timer dispatch.
This could resolve HW deadlocks where a unit downstream of the VS is waiting for more input, the VS has one vertex queued up but not dispatched because it hopes to get one more vertex for 2x4 dispatch, and software isn't handing more vertices down because it's waiting for rendering to complete. The B-Spec says you should always have this bit set. Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e52a277814c0..134973f77069 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4725,6 +4725,11 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
ring->space += ring->Size;
}
+ if (IS_I9XX(dev) && !IS_GEN3(dev)) {
+ I915_WRITE(MI_MODE,
+ (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
+ }
+
return 0;
}