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authorDamien Lespiau <damien.lespiau@intel.com>2015-02-09 19:33:21 +0000
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-13 23:28:36 +0100
commite2db7071f14b7ac095a24448e9edd036ba332da3 (patch)
tree1a20aeeea7f1a98a5dda8a38ff0321b0dfc1db19 /drivers/gpu/drm/i915/i915_reg.h
parent2caa3b260aa6a3d015352c07d1bce1461825fa6c (diff)
drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ecc14f558744..8c9e15073e38 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6209,6 +6209,7 @@ enum skl_disp_power_wells {
#define GEN9_HALF_SLICE_CHICKEN5 0xe188
#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
+#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
#define GEN8_ROW_CHICKEN 0xe4f0
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)