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authorJesse Barnes <jbarnes@virtuousgeek.org>2013-10-11 12:09:29 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-11 23:32:32 +0200
commite8cde23b4607e19bd079a8173393a0d16aadfe31 (patch)
tree9662095e3f5b0f6854efd3d94851ca0e652d9c79 /drivers/gpu/drm/i915/i915_suspend.c
parentfbf49ea21bd4f2ed88d678f7fc8b34a7dd0a7460 (diff)
drm/i915: don't save/restore CACHE_MODE_0 on gen7+
On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather than restoring CACHE_MODE_0. Don't do that. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 3538370e3a47..a088f1f46bdb 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -369,7 +369,8 @@ int i915_save_state(struct drm_device *dev)
intel_disable_gt_powersave(dev);
/* Cache mode state */
- dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
+ if (INTEL_INFO(dev)->gen < 7)
+ dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
/* Memory Arbitration state */
dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
@@ -418,7 +419,9 @@ int i915_restore_state(struct drm_device *dev)
}
/* Cache mode state */
- I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
+ if (INTEL_INFO(dev)->gen < 7)
+ I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
+ 0xffff0000);
/* Memory arbitration state */
I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);