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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-29 19:33:42 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-29 21:51:14 +0200
commit627eb5a318a6caca2145d3c7195b084c59b291d9 (patch)
tree9ecbdf9215c97754566be5cdaecb8722e8d66119 /drivers/gpu/drm/i915/intel_ddi.c
parent33d29b145305641f2c693b759cac468e0c87ab4d (diff)
drm/i915: hw state readout support for pipe_config->fdi_lanes
v2: Introduce some nice #defines for the FDI lane width fields and put them to good use. Suggested by Ville. v3: Fixup the mask vs. shift copy&pasta fail Imre Deak spotted, and use the shift #define also in the mask. Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c9c4741020df..72941f94c830 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -182,7 +182,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
/* Enable the PCH Receiver FDI PLL */
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
- ((intel_crtc->config.fdi_lanes - 1) << 19);
+ FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
POSTING_READ(_FDI_RXA_CTL);
udelay(220);