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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-20 10:15:30 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-20 10:15:30 -0700
commit43813f399c72aa22e01a680559c1cb5274bf2140 (patch)
tree933c0e7c445b9c3478b5a0db06a162d0d39f00f2 /drivers/gpu/drm/i915/intel_display.c
parenta552f0af753eb4b5bbbe9eff205fe874b04c4583 (diff)
parent0b7af262aba912f52bc6ef76f1bc0960b01b8502 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (24 commits) agp/intel: Make intel_i965_mask_memory use dma_addr_t for physical addresses agp: add user mapping support to ATI AGP bridge. drm/i915: enable GEM on PAE. drm/radeon: fix unused variables warning agp: switch AGP to use page array instead of unsigned long array agpgart: detected ALi M???? chipset with M1621 drm/radeon: command stream checker for r3xx-r5xx hardware drm/radeon: Fully initialize LVDS info also when we can't get it from the ROM. radeon: Fix CP byte order on big endian architectures with KMS. agp/uninorth: Handle user memory types. drm/ttm: Add some powerpc cache flush code. radeon: Enable modesetting on non-x86. drm/radeon: Respect AGP cant_use_aperture flag. drm: EDID endianness fixes. drm/radeon: this VRAM vs aperture test is wrong, just remove it. drm/ttm: fix an error path to exit function correctly drm: Apply "Memory fragmentation from lost alignment blocks" ttm: Return -ERESTART when a signal interrupts bo eviction. drm: Remove memory debugging infrastructure. drm/i915: Clear fence register on tiling stride change. ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c20
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 028f5b66e3d8..3e1c78162119 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -828,19 +828,31 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
mutex_lock(&dev->struct_mutex);
- ret = i915_gem_object_pin(intel_fb->obj, alignment);
+ ret = i915_gem_object_pin(obj, alignment);
if (ret != 0) {
mutex_unlock(&dev->struct_mutex);
return ret;
}
- ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
+ ret = i915_gem_object_set_to_gtt_domain(obj, 1);
if (ret != 0) {
- i915_gem_object_unpin(intel_fb->obj);
+ i915_gem_object_unpin(obj);
mutex_unlock(&dev->struct_mutex);
return ret;
}
+ /* Pre-i965 needs to install a fence for tiled scan-out */
+ if (!IS_I965G(dev) &&
+ obj_priv->fence_reg == I915_FENCE_REG_NONE &&
+ obj_priv->tiling_mode != I915_TILING_NONE) {
+ ret = i915_gem_object_get_fence_reg(obj);
+ if (ret != 0) {
+ i915_gem_object_unpin(obj);
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+ }
+ }
+
dspcntr = I915_READ(dspcntr_reg);
/* Mask out pixel format bits in case we change it */
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
@@ -860,7 +872,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
break;
default:
DRM_ERROR("Unknown color depth\n");
- i915_gem_object_unpin(intel_fb->obj);
+ i915_gem_object_unpin(obj);
mutex_unlock(&dev->struct_mutex);
return -EINVAL;
}