diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-24 16:42:43 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-24 16:42:43 -0700 |
| commit | 6467a71c56934251f3c917bd4386387c2a97b41e (patch) | |
| tree | 09f930fda8c6c555d488971d76e728846be55650 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 18020a0d8cccad0d3642219d6aef789420c04c1f (diff) | |
| parent | 6e6c822868f113dabe3c33bdd91e883cc28fa11b (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Stop trying to use ACPI lid status to determine LVDS connection.
drm/intel: fix up set_tiling for untiled->tiled transition
drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
agp/intel: Don't do the chipset flush on Sandybridge.
agp/intel: Respect the GTT size on Sandybridge for scratch page setup.
drm/i915: fix small leak on overlay error path
drm/i915: Avoid NULL deref in get_pages() unwind after error.
drm/i915: Fix check with IS_GEN6
drivers/gpu/drm/i915/intel_bios.c: fix continuation line formats
drm/i915: Enable VS timer dispatch.
drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers
drm/i915: remove an unnecessary wait_request()
drm/i915: Don't bother with the BKL for GEM ioctls.
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9cd6de5f9906..58fc7fa0eb1d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1032,7 +1032,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) /* enable it... */ fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; if (IS_I945GM(dev)) - fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */ + fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; if (obj_priv->tiling_mode != I915_TILING_NONE) @@ -4717,6 +4717,20 @@ void intel_init_clock_gating(struct drm_device *dev) * specs, but enable as much else as we can. */ if (HAS_PCH_SPLIT(dev)) { + uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; + + if (IS_IRONLAKE(dev)) { + /* Required for FBC */ + dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; + /* Required for CxSR */ + dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; + + I915_WRITE(PCH_3DCGDIS0, + MARIUNIT_CLOCK_GATE_DISABLE | + SVSMUNIT_CLOCK_GATE_DISABLE); + } + + I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); return; } else if (IS_G4X(dev)) { uint32_t dspclk_gate; |