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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-09-01 15:08:06 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2016-09-07 13:55:33 -0700
commitdfa104803523a57711d575dfca898c0b3761f5eb (patch)
treeb17d1c292b72c0cdf489967949a00adb1762630b /drivers/gpu/drm/i915/intel_dp.c
parent23f889bdf6ee5cfff012d8b09f6bec920c691696 (diff)
drm/i915: Don't pass crtc_state to intel_dp_set_link_params()
Decouple intel_dp_set_link_params() from struct intel_crtc_state. This will be useful for implementing DP upfront link training. v2: * Rebased on atomic state changes (Manasi) Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4b14565afb3d..75ac62fa6bf5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1641,11 +1641,12 @@ found:
}
void intel_dp_set_link_params(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+ int link_rate, uint8_t lane_count,
+ bool link_mst)
{
- intel_dp->link_rate = pipe_config->port_clock;
- intel_dp->lane_count = pipe_config->lane_count;
- intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
+ intel_dp->link_rate = link_rate;
+ intel_dp->lane_count = lane_count;
+ intel_dp->link_mst = link_mst;
}
static void intel_dp_prepare(struct intel_encoder *encoder,
@@ -1658,7 +1659,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- intel_dp_set_link_params(intel_dp, pipe_config);
+ intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
+ pipe_config->lane_count,
+ intel_crtc_has_type(pipe_config,
+ INTEL_OUTPUT_DP_MST));
/*
* There are four kinds of DP registers: