diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-10 18:09:59 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-10 23:46:16 +0200 |
| commit | 27c6f0a5897c06417e39f2d20a783f84a54cb0b3 (patch) | |
| tree | 9da08f6c1432e3a2f257b9f42ecceb3891c63ea2 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 1e6210f45d95f1db7831072b7be64f9562280df1 (diff) | |
drm/i915: don't implement WaDisableEarlyCull for Haswell
Introduced in commit 87f8020ec9e3069597746040a4e8655189bc0c1a:
drm/i915: implement WaDisableEarlyCull for VLV and IVB
Notice that the original patch sent to the mailing list did not
include the Haswell chunk, it was added later.
The bit set by the commit does not exist on Haswell machines (at least
that's what the documentation says). Also, the commit gives me a GPU
hang every time we're loading the driver. So let's revert the Haswell
chunk, making the patch do only what its title actually says.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index eb757e5f2d87..07da990eb77d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3470,10 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) */ I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* WaDisableEarlyCull */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); - /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |