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| author | Mark Brown <broonie@kernel.org> | 2015-01-07 17:30:17 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-01-07 17:30:17 +0000 |
| commit | 1285c3fefaddedf5358f52cfde3c2b64d8086a04 (patch) | |
| tree | 361f556d6b400e8cb6d16738142db2f69f63ef2f /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 6b038c8d2b99b552f0b025c8a134f8a3c417a3e7 (diff) | |
| parent | b1940cd21c0f4abdce101253e860feff547291b0 (diff) | |
Merge tag 'v3.19-rc3' into spi-sh-msiof
Linux 3.19-rc3
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9f445e9a75d1..c7bc93d28d84 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -362,12 +362,15 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; /* * TLB invalidate requires a post-sync write. */ flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; + /* Workaround: we must issue a pipe_control with CS-stall bit * set before a pipe_control command that has the state cache * invalidate bit set. */ |