MLK-18618-1: hdp: Add faile check for get_table_row

Add faile check for get_table_row.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>

2 files changed, 33 insertions, 41 deletions

diff --git a/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c b/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
index 8580ab964c43..471039fb6a13 100644
--- a/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
+++ b/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
@@ -59,7 +59,8 @@ int phy_cfg_hdp_ss28fdsoi(state_struct *state,
 	const int phy_reset_workaround = 0;
 	u32 vco_freq_khz;
 	unsigned char i;
-	u32 row, feedback_factor;
+	u32 feedback_factor;
+	int row;
 	u32 reg_val;
 	int pixel_freq_khz = mode->clock;
 	u32 character_clock_ratio_num = 1;
@@ -255,16 +256,15 @@ int phy_cfg_hdp_ss28fdsoi(state_struct *state,
 
 	/* Check if row was found */
 	ftemp = pixel_freq_khz;
-	if (row + 1) {
-		DRM_INFO
-		    ("Pixel clock frequency (%u kHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
-		     ftemp, bpp, row);
-	} else {
-		DRM_INFO
-		    ("Pixel clock frequency (%u kHz) not supported for this color depth (%0d-bit), row=%d\n",
+	if (row == -1) {
+		DRM_WARN("Pixel clock frequency (%u kHz) not supported for this color depth (%0d-bit), row=%d\n",
 		     ftemp, bpp, row);
 		return 0;
 	}
+	DRM_INFO
+		("Pixel clock frequency (%u kHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
+		 ftemp, bpp, row);
+
 	character_freq_khz =
 	    pixel_freq_khz * character_clock_ratio_num /
 	    character_clock_ratio_den;
@@ -346,13 +346,13 @@ int phy_cfg_hdp_ss28fdsoi(state_struct *state,
 			  PLL_FEEDBACK_DIV_TOTAL,
 			  pll_feedback_divider_total.value);
 	ftemp = vco_freq_khz;
-	if (row + 1) {
-		DRM_INFO
-		    ("VCO frequency (%u kHz) is supported. Settings found in row %0d\n",
-		     ftemp, row);
-	} else {
-		DRM_INFO("VCO frequency (%u kHz) not supported\n", ftemp);
+	if (row == -1) {
+		DRM_WARN("VCO frequency (%u kHz) not supported\n", ftemp);
+		return 0;
 	}
+	DRM_INFO
+	    ("VCO frequency (%u kHz) is supported. Settings found in row %0d\n",
+	     ftemp, row);
 
 	/* Extract particular values from the ss28fdsoi_hdmitx_pll_tuning_table table */
 	set_field_value(&voltage_to_current_coarse,
diff --git a/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
index c84837c259a5..3b11545dad84 100644
--- a/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
+++ b/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
@@ -74,7 +74,7 @@ int phy_cfg_hdp_t28hpc(state_struct *state,
 	const int phy_reset_workaround = 1;
 	u32 vco_freq_khz;
 	unsigned char k;
-	unsigned char row;
+	int row;
 	u32 feedback_factor;
 	u32 reg_val;
 	u32 pll_feedback_divider_total;
@@ -257,16 +257,14 @@ int phy_cfg_hdp_t28hpc(state_struct *state,
 				  feedback_factor);
 
 		/* Check if row was found */
-		if (row + 1) {
-			DRM_INFO
-			    ("Pixel clock frequency (%d KHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
-			     pixel_freq_khz, bpp, row);
-		} else {
-			DRM_INFO
-			    ("Pixel clock frequency (%d KHz) not supported for this color depth (%0d-bit)\n",
+		if (row == -1) {
+			DRM_WARN("Pixel clock frequency (%d KHz) not supported for this color depth (%0d-bit)\n",
 			     pixel_freq_khz, bpp);
 			return 0;
 		}
+		DRM_INFO
+		    ("Pixel clock frequency (%d KHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
+		     pixel_freq_khz, bpp, row);
 
 		/* Extract particular values from the
 		 * t28hpc_hdmitx_clock_control_table_pixel_in table */
@@ -344,15 +342,13 @@ int phy_cfg_hdp_t28hpc(state_struct *state,
 				  T7_PLL_FEEDBACK_DIV_TOTAL,
 				  pll_feedback_divider_total);
 
-		if (row + 1) {
-			DRM_INFO
-			    ("VCO frequency (%d KHz) is supported. Settings found in row %0d\n",
-			     vco_freq_khz, row);
-		} else {
-			DRM_INFO("VCO frequency (%d KHz) not supported\n",
+		if (row == -1) {
+			DRM_WARN("VCO frequency (%d KHz) not supported\n",
 			       vco_freq_khz);
 			return 0;
 		}
+		DRM_INFO ("VCO frequency (%d KHz) is supported. Settings found in row %0d\n",
+			     vco_freq_khz, row);
 
 		/* Extract particular values from
 		 * the t28hpc_hdmitx_pll_tuning_table_pixel_in table */
@@ -404,16 +400,14 @@ int phy_cfg_hdp_t28hpc(state_struct *state,
 				  feedback_factor);
 
 		/* Check if row was found */
-		if (row + 1) {
-			DRM_INFO
-			    ("Pixel clock frequency (%d KHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
-			     pixel_freq_khz, bpp, row);
-		} else {
-			DRM_INFO
-			    ("Pixel clock frequency (%d KHz) not supported for this color depth (%0d-bit)\n",
+		if (row == -1) {
+			DRM_WARN("Pixel clock frequency (%d KHz) not supported for this color depth (%0d-bit)\n",
 			     pixel_freq_khz, bpp);
 			return 0;
 		}
+		DRM_INFO
+			 ("Pixel clock frequency (%d KHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
+			     pixel_freq_khz, bpp, row);
 
 		/* Extract particular values from
 		 * the t28hpc_hdmitx_clock_control_table_pixel_out table */
@@ -501,15 +495,13 @@ int phy_cfg_hdp_t28hpc(state_struct *state,
 				  T9_PLL_FEEDBACK_DIV_TOTAL,
 				  pll_feedback_divider_total);
 
-		if (row + 1) {
-			DRM_INFO
-			    ("VCO frequency (%d KHz) is supported. Settings found in row %0d\n",
-			     vco_freq_khz, row);
-		} else {
-			DRM_INFO("VCO frequency (%d KHz) not supported\n",
+		if (row == -1) {
+			DRM_WARN("VCO frequency (%d KHz) not supported\n",
 			       vco_freq_khz);
 			return 0;
 		}
+		DRM_INFO("VCO frequency (%d KHz) is supported. Settings found in row %0d\n",
+			     vco_freq_khz, row);
 
 		/* Extract particular values from
 		 * the t28hpc_hdmitx_pll_tuning_table_pixel_out table. */