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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-19 18:40:36 -1000
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-19 18:40:36 -1000
commit0c9bc275304fd1c46584e1e651ce6698e5d61042 (patch)
tree6bd11f906b24465e6020080dfc7cefcef4aea874 /drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
parentf1d702487b3bc16466ad9b4e5c76277b6829d34c (diff)
parent884d6147ba19640a40fb45efe64360cdf92cac27 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This looks bigger than it is, as one of the nouveau firmware fixes ("drm/gf100-/gr: report class data to host on fwmthd failure") regenerates a bunch of the firmware files after changing the assembly by a few lines, without that, its more of a 36 files changed, 370 insertions(+), 129 deletions(-) It contains some vt.c fixes acked by Greg, for rare hard hangs on i915 loading, that also fixes hangs on reload and spurious register write errors. drm core: one fix for uninit memory nouveau: displayport rework caused a few regressions, Ben has been fixing them as the appear, along with some other fixes radeon: pageflipping regression fix, deep color fix, mode validation fixes i915: fbc disable, vga console kick off, backlight fix, divide-by-zero fix" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (33 commits) drm: fix uninitialized acquire_ctx fields (v2) drm/radeon: Fix radeon_irq_kms_pflip_irq_get/put() imbalance Revert "drm/radeon: remove drm_vblank_get|put from pflip handling" drm/radeon: improve dvi_mode_valid drm/radeon: update mode_valid testing for DP drm/radeon: Use dce5/6 hdmi deep color clock setup also on dce8+ drm/nouveau/disp: fix oops in destructor with headless cards drm/gf117/i2c: no aux channels on this chipset drm/nouveau/doc: update the thermal documentation drm/nouveau/pwr: fix typo in fifo wrap handling drm/nv50/disp: fix a potential oops in supervisor handling drm/nouveau/disp/dp: don't touch link config after success drm/nouveau/kms: reference vblank for crtc during pageflip. drm/gk104/fb/ram: fixups from an earlier search+replace drm/nv50/gr: remove an unneeded write while initialising PGRAPH drm/nv50/gr: fix overlap while zeroing zcull regions drm/gf100-/gr: report class data to host on fwmthd failure drm/gk104/ibus: increase various random timeouts drm/gk104/clk: only touch divider for mode we'll be using drm/radeon: Bypass hw lut's for > 8 bpc framebuffer scanout. ...
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c41
1 files changed, 32 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index bf7bdb1f291e..aa0838916354 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -789,17 +789,40 @@ nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
static void
nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
{
- u32 ustat = nv_rd32(priv, 0x409c18);
+ u32 stat = nv_rd32(priv, 0x409c18);
- if (ustat & 0x00000001)
- nv_error(priv, "CTXCTL ucode error\n");
- if (ustat & 0x00080000)
- nv_error(priv, "CTXCTL watchdog timeout\n");
- if (ustat & ~0x00080001)
- nv_error(priv, "CTXCTL 0x%08x\n", ustat);
+ if (stat & 0x00000001) {
+ u32 code = nv_rd32(priv, 0x409814);
+ if (code == E_BAD_FWMTHD) {
+ u32 class = nv_rd32(priv, 0x409808);
+ u32 addr = nv_rd32(priv, 0x40980c);
+ u32 subc = (addr & 0x00070000) >> 16;
+ u32 mthd = (addr & 0x00003ffc);
+ u32 data = nv_rd32(priv, 0x409810);
+
+ nv_error(priv, "FECS MTHD subc %d class 0x%04x "
+ "mthd 0x%04x data 0x%08x\n",
+ subc, class, mthd, data);
- nvc0_graph_ctxctl_debug(priv);
- nv_wr32(priv, 0x409c20, ustat);
+ nv_wr32(priv, 0x409c20, 0x00000001);
+ stat &= ~0x00000001;
+ } else {
+ nv_error(priv, "FECS ucode error %d\n", code);
+ }
+ }
+
+ if (stat & 0x00080000) {
+ nv_error(priv, "FECS watchdog timeout\n");
+ nvc0_graph_ctxctl_debug(priv);
+ nv_wr32(priv, 0x409c20, 0x00080000);
+ stat &= ~0x00080000;
+ }
+
+ if (stat) {
+ nv_error(priv, "FECS 0x%08x\n", stat);
+ nvc0_graph_ctxctl_debug(priv);
+ nv_wr32(priv, 0x409c20, stat);
+ }
}
static void