diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-10 04:10:24 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-10 05:13:24 +1000 |
| commit | 4acfd707e28c820ba8ed8c12b497413a133d8c8f (patch) | |
| tree | 4c2bd62829b85c31bc5ad656e7140ed599038163 /drivers/gpu/drm/nouveau/nv50_fence.c | |
| parent | b2c817031bc99d6e809fa10dcd8bf709b61d088d (diff) | |
drm/nouveau/dma: audit and version NV_DMA classes
The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fence.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_fence.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index 7bb22a95159f..195cf51a7c31 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c @@ -51,14 +51,13 @@ nv50_fence_context_new(struct nouveau_channel *chan) fctx->base.read = nv10_fence_read; fctx->base.sync = nv17_fence_sync; - ret = nvif_object_init(chan->object, NULL, NvSema, - NV_DMA_IN_MEMORY_CLASS, - &(struct nv_dma_class) { - .flags = NV_DMA_TARGET_VRAM | - NV_DMA_ACCESS_RDWR, + ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY, + &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, .start = start, .limit = limit, - }, sizeof(struct nv_dma_class), + }, sizeof(struct nv_dma_v0), &fctx->sema); /* dma objects for display sync channel semaphore blocks */ @@ -68,13 +67,12 @@ nv50_fence_context_new(struct nouveau_channel *chan) u32 limit = start + bo->bo.mem.size - 1; ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i, - NV_DMA_IN_MEMORY_CLASS, - &(struct nv_dma_class) { - .flags = NV_DMA_TARGET_VRAM | - NV_DMA_ACCESS_RDWR, + NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, .start = start, .limit = limit, - }, sizeof(struct nv_dma_class), + }, sizeof(struct nv_dma_v0), &fctx->head[i]); } |