diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-16 15:48:00 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-16 15:48:00 -0800 |
commit | 796e1c55717e9a6ff5c81b12289ffa1ffd919b6f (patch) | |
tree | 27ce45cb1227156b72c641dbcbf2b399d23ba63d /drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | |
parent | 8c334ce8f0fec7122fc3059c52a697b669a01b41 (diff) | |
parent | 45ee2dbc65cbf6910892c480e6f428be342fa733 (diff) |
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"This is the main drm pull, it has a shared branch with some alsa
crossover but everything should be acked by relevant people.
New drivers:
- ATMEL HLCDC driver
- designware HDMI core support (used in multiple SoCs).
core:
- lots more atomic modesetting work, properties and atomic ioctl
(hidden under option)
- bridge rework allows support for Samsung exynos chromebooks to
work finally.
- some more panels supported
i915:
- atomic plane update support
- DSI uses shared DSI infrastructure
- Skylake basic support is all merged now
- component framework used for i915/snd-hda interactions
- write-combine cpu memory mappings
- engine init code refactored
- full ppgtt enabled where execlists are enabled.
- cherryview rps/gpu turbo and pipe CRC support.
radeon:
- indirect draw support for evergreen/cayman
- SMC and manual fan control for SI/CI
- Displayport audio support
amdkfd:
- SDMA usermode queue support
- replace suballocator usage with more suitable one
- rework for allowing interfacing to more than radeon
nouveau:
- major renaming in prep for later splitting work
- merge arm platform driver into nouveau
- GK20A reclocking support
msm:
- conversion to atomic modesetting
- YUV support for mdp4/5
- eDP support
- hw cursor for mdp5
tegra:
- conversion to atomic modesetting
- better suspend/resume support for child devices
rcar-du:
- interlaced support
imx:
- move to using dw_hdmi shared support
- mode_fixup support
sti:
- DVO support
- HDMI infoframe support
exynos:
- refactoring and cleanup, removed lots of internal unnecessary
abstraction
- exynos7 DECON display controller support
Along with the usual bunch of fixes, cleanups etc"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (724 commits)
drm/radeon: fix voltage setup on hawaii
drm/radeon/dp: Set EDP_CONFIGURATION_SET for bridge chips if necessary
drm/radeon: only enable kv/kb dpm interrupts once v3
drm/radeon: workaround for CP HW bug on CIK
drm/radeon: Don't try to enable write-combining without PAT
drm/radeon: use 0-255 rather than 0-100 for pwm fan range
drm/i915: Clamp efficient frequency to valid range
drm/i915: Really ignore long HPD pulses on eDP
drm/exynos: Add DECON driver
drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL
drm/i915: Insert a command barrier on BLT/BSD cache flushes
drm/i915: Drop vblank wait from intel_dp_link_down
drm/exynos: fix NULL pointer reference
drm/exynos: remove exynos_plane_dpms
drm/exynos: remove mode property of exynos crtc
drm/exynos: Remove exynos_plane_dpms() call with no effect
drm/i915: Squelch overzealous uncore reset WARN_ON
drm/i915: Take runtime pm reference on hangcheck_info
drm/i915: Correct the IOSF Dev_FN field for IOSF transfers
drm/exynos: fix DMA_ATTR_NO_KERNEL_MAPPING usage
...
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c new file mode 100644 index 000000000000..94a1ca45e94a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -0,0 +1,204 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <subdev/bios.h> +#include <subdev/bus.h> +#include <subdev/gpio.h> +#include <subdev/i2c.h> +#include <subdev/clk.h> +#include <subdev/devinit.h> +#include <subdev/mc.h> +#include <subdev/timer.h> +#include <subdev/fb.h> +#include <subdev/instmem.h> +#include <subdev/mmu.h> + +#include <engine/dmaobj.h> +#include <engine/fifo.h> +#include <engine/sw.h> +#include <engine/gr.h> +#include <engine/disp.h> + +int +nv10_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0x10: + device->cname = "NV10"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x15: + device->cname = "NV15"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x16: + device->cname = "NV16"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x1a: + device->cname = "nForce"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x11: + device->cname = "NV11"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x17: + device->cname = "NV17"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x1f: + device->cname = "nForce2"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x18: + device->cname = "NV18"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + default: + nv_fatal(device, "unknown Celsius chipset\n"); + return -EINVAL; + } + + return 0; +} |