diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-06-25 17:56:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-27 19:40:05 -0400 |
| commit | a9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch) | |
| tree | 82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm/radeon/ppsmc.h | |
| parent | a0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff) | |
drm/radeon/kms: add dpm support for SI (v7)
This adds dpm support for SI asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ppsmc.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/ppsmc.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h index 0f6ccce27a35..8fb1113a8fd7 100644 --- a/drivers/gpu/drm/radeon/ppsmc.h +++ b/drivers/gpu/drm/radeon/ppsmc.h @@ -26,6 +26,9 @@ #pragma pack(push, 1) #define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 +#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 @@ -36,17 +39,22 @@ #define PPSMC_SYSTEMFLAG_GDDR5 0x04 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 +#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 #define PPSMC_DISPLAY_WATERMARK_LOW 0 #define PPSMC_DISPLAY_WATERMARK_HIGH 1 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 #define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 #define PPSMC_Result_OK ((uint8_t)0x01) #define PPSMC_Result_Failed ((uint8_t)0xFF) @@ -80,9 +88,14 @@ typedef uint8_t PPSMC_Result; #define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) #define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) +#define PPSMC_FlushDataCache ((uint8_t)0x80) #define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) #define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) +#define PPSMC_MSG_EnableDTE ((uint8_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint8_t)0x88) +#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) +#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) /* TN */ #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) |