diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2014-09-17 16:25:55 +0900 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-09-18 18:57:07 -0400 |
| commit | 897eba827e8659a03a1b2f4e74389691f824783f (patch) | |
| tree | 8ba4a99a4e795abf9dfa943f50b9c9dcebcc5dfa /drivers/gpu/drm/radeon/radeon_drv.c | |
| parent | 64d8ee59577a2b1de73cc40c2ec661bddf71e8b0 (diff) | |
drm/radeon: Disable HDP flush before every CS again for < r600
It was causing display corruption with R300 generation GPUs at least.
Reported-and-Tested-by: Mikael Pettersson <mikpelinux@gmail.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_drv.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 8df888908833..e8545be7d584 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -83,7 +83,7 @@ * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG * 2.39.0 - Add INFO query for number of active CUs * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting - * CS to GPU + * CS to GPU on >= r600 */ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 40 |