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authorChristian König <christian.koenig@amd.com>2014-07-30 17:18:12 +0200
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:42 -0400
commitf1d2a26b506e9dc7bbe94fae40da0a0d8dcfacd0 (patch)
treed83c6738c86a7f55791c62a71306e249fe8e37c8 /drivers/gpu/drm/radeon/si.c
parentf069dc1dbc1e17b04b2ec65f65d1c9e9af667ff5 (diff)
drm/radeon: set VM base addr using the PFP v2
Seems to make VM flushes more stable on SI and CIK. v2: only use the PFP on the GFX ring on CIK Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6741804e4af2..806bed1758d6 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5013,7 +5013,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
/* write new base address */
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
WRITE_DATA_DST_SEL(0)));
if (vm->id < 8) {