diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-03-26 13:32:21 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-05 23:09:33 +0200 |
| commit | 91eded9b481e61913d98142927b559af33a180a7 (patch) | |
| tree | bcab00eb979434cc358abe43a4f4cf2633d43f06 /drivers/gpu/drm/tegra/sor.c | |
| parent | dbb3f2f751069bc757fbdbe8911a7e784e850b24 (diff) | |
drm/tegra: dc - Compute shift clock divider in output drivers
The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b2151ea679f0..078bd37e6c34 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -861,13 +861,14 @@ static int tegra_output_sor_disable(struct tegra_output *output) } static int tegra_output_sor_setup_clock(struct tegra_output *output, - struct clk *clk, unsigned long pclk) + struct clk *clk, unsigned long pclk, + unsigned int *div) { struct tegra_sor *sor = to_sor(output); int err; /* round to next MHz */ - pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000; + pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000; err = clk_set_parent(clk, sor->clk_parent); if (err < 0) { @@ -877,11 +878,12 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output, err = clk_set_rate(sor->clk_parent, pclk); if (err < 0) { - dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n", - pclk * 2); + dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk); return err; } + *div = 0; + return 0; } |