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authorThierry Reding <treding@nvidia.com>2014-12-19 15:09:16 +0100
committerThierry Reding <treding@nvidia.com>2015-01-27 10:14:54 +0100
commit76d59ed049197bdaaa24c0e061a105af6ce74457 (patch)
tree227de1687644dc5910cd0596bf21f84c15615216 /drivers/gpu/drm/tegra
parent82f1511c35643575e6f28013a3bb348e35676491 (diff)
drm/tegra: dc: Use atomic clock state in modeset
All clock state is now stored in the display controller's atomic state, so the output drivers no longer need to call back into the display controller driver to set up the clock. This is also required to make sure no hardware changes are made before validating a configuration. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/dc.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index b905a4e2bdf9..5d6c00abd203 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1213,12 +1213,49 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc,
return 0;
}
+static void tegra_dc_commit_state(struct tegra_dc *dc,
+ struct tegra_dc_state *state)
+{
+ u32 value;
+ int err;
+
+ err = clk_set_parent(dc->clk, state->clk);
+ if (err < 0)
+ dev_err(dc->dev, "failed to set parent clock: %d\n", err);
+
+ /*
+ * Outputs may not want to change the parent clock rate. This is only
+ * relevant to Tegra20 where only a single display PLL is available.
+ * Since that PLL would typically be used for HDMI, an internal LVDS
+ * panel would need to be driven by some other clock such as PLL_P
+ * which is shared with other peripherals. Changing the clock rate
+ * should therefore be avoided.
+ */
+ if (state->pclk > 0) {
+ err = clk_set_rate(state->clk, state->pclk);
+ if (err < 0)
+ dev_err(dc->dev,
+ "failed to set clock rate to %lu Hz\n",
+ state->pclk);
+ }
+
+ DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
+ state->div);
+ DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
+
+ value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
+ tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
+}
+
static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct tegra_dc_state *state = to_dc_state(crtc->state);
struct tegra_dc *dc = to_tegra_dc(crtc);
u32 value;
+ tegra_dc_commit_state(dc, state);
+
/* program display mode */
tegra_dc_set_timings(dc, mode);