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authorLaurentiu Palcu <laurentiu.palcu@nxp.com>2018-02-20 15:06:49 +0200
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commite1a3e1ec982008b6a02e4bf0cf67eac529b5bb03 (patch)
treededaf6fe0ce61e07dab9ce5268a7f3eb34ca79de /drivers/gpu/imx/dcss
parent6eff100de6d7ce17c90e16e0aca3109098d56db5 (diff)
MLK-17634-16: drm: imx: dcss: make 10-bit formats work with HDR
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'drivers/gpu/imx/dcss')
-rw-r--r--drivers/gpu/imx/dcss/dcss-dpr.c7
-rw-r--r--drivers/gpu/imx/dcss/dcss-dtrc.c10
-rw-r--r--drivers/gpu/imx/dcss/dcss-hdr10.c10
-rw-r--r--drivers/gpu/imx/dcss/dcss-scaler.c3
4 files changed, 21 insertions, 9 deletions
diff --git a/drivers/gpu/imx/dcss/dcss-dpr.c b/drivers/gpu/imx/dcss/dcss-dpr.c
index 7c59f8e369fb..cfe0b8121685 100644
--- a/drivers/gpu/imx/dcss/dcss-dpr.c
+++ b/drivers/gpu/imx/dcss/dcss-dpr.c
@@ -239,7 +239,7 @@ static u32 dcss_dpr_x_pix_wide_adjust(struct dcss_dpr_ch *ch, u32 pix_wide,
pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];
if (pix_format == DRM_FORMAT_P010)
- pix_wide *= 10 / 8;
+ pix_wide = pix_wide * 10 / 8;
div_64byte_mod = pix_wide % pix_in_64byte;
offset = (div_64byte_mod == 0) ? 0 : (pix_in_64byte - div_64byte_mod);
@@ -274,6 +274,9 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
pix_format == DRM_FORMAT_P010)
max_planes = 2;
+ if (pix_format == DRM_FORMAT_P010)
+ adj_w = adj_w * 10 / 8;
+
for (plane = 0; plane < max_planes; plane++) {
yres = plane == 1 ? yres >> 1 : yres;
@@ -281,7 +284,7 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
pix_y_high = dcss_dpr_y_pix_high_adjust(ch, yres, pix_format);
/* DTRC may need another width alignment. If it does, use it. */
- if (pix_x_wide != adj_w)
+ if (pix_x_wide < adj_w)
pix_x_wide = adj_w;
if (pix_y_high != adj_h)
diff --git a/drivers/gpu/imx/dcss/dcss-dtrc.c b/drivers/gpu/imx/dcss/dcss-dtrc.c
index 8589627ab5a0..e862308a881f 100644
--- a/drivers/gpu/imx/dcss/dcss-dtrc.c
+++ b/drivers/gpu/imx/dcss/dcss-dtrc.c
@@ -330,6 +330,7 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
int bank;
u32 old_xres, old_yres, xres, yres;
u32 pix_depth;
+ u16 width_align = 0;
if (ch_num == 0)
return;
@@ -357,10 +358,11 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
/*
* Image original size is aligned:
- * - 128 pixels for width;
+ * - 128 pixels for width (8-bit) or 256 (10-bit);
* - 8 lines for height;
*/
- if (xres == old_xres && !(xres & 0x7f) &&
+ width_align = ch->pix_format == DRM_FORMAT_P010 ? 0xff : 0x7f;
+ if (xres == old_xres && !(xres & width_align) &&
yres == old_yres && !(yres & 0xf)) {
ch->dctl &= ~CROPPING_EN;
goto exit;
@@ -368,9 +370,9 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
/* align the image size: down align for compressed formats */
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->x1)
- xres = xres & ~0x7f;
+ xres = xres & ~width_align;
else
- xres = (xres - 1 + 0x7f) & ~0x7f;
+ xres = (xres - 1 + width_align) & ~width_align;
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->y1)
yres = yres & ~0xf;
diff --git a/drivers/gpu/imx/dcss/dcss-hdr10.c b/drivers/gpu/imx/dcss/dcss-hdr10.c
index 609a09a3511e..066299dbd668 100644
--- a/drivers/gpu/imx/dcss/dcss-hdr10.c
+++ b/drivers/gpu/imx/dcss/dcss-hdr10.c
@@ -598,7 +598,8 @@ static u64 dcss_hdr10_get_desc(struct dcss_hdr10_pipe_cfg *ipipe_cfg,
{
u32 ipipe_desc, opipe_desc;
- ipipe_desc = dcss_hdr10_pipe_desc(ipipe_cfg);
+ ipipe_desc = dcss_hdr10_pipe_desc(ipipe_cfg) & (~HDR10_BPC_MASK);
+ ipipe_desc |= 2 << HDR10_BPC_POS;
opipe_desc = dcss_hdr10_pipe_desc(opipe_cfg);
return (ipipe_desc & 0xFFFF) |
@@ -631,6 +632,11 @@ void dcss_hdr10_setup(struct dcss_soc *dcss, int ch_num,
u64 desc = dcss_hdr10_get_desc(ipipe_cfg, opipe_cfg);
dcss_hdr10_pipe_setup(dcss, ch_num, desc);
- dcss_hdr10_pipe_setup(dcss, OPIPE_CH_NO, desc);
+
+ /*
+ * Input pipe configuration doesn't matter for configuring the output
+ * pipe. So, will just mask off the input part of the descriptor.
+ */
+ dcss_hdr10_pipe_setup(dcss, OPIPE_CH_NO, desc | 0xffff);
}
EXPORT_SYMBOL(dcss_hdr10_setup);
diff --git a/drivers/gpu/imx/dcss/dcss-scaler.c b/drivers/gpu/imx/dcss/dcss-scaler.c
index 002cfc4355e7..6b76f3a3ea4d 100644
--- a/drivers/gpu/imx/dcss/dcss-scaler.c
+++ b/drivers/gpu/imx/dcss/dcss-scaler.c
@@ -615,7 +615,8 @@ void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format,
dcss_scaler_yuv_coef_set(dcss, ch_num);
- /* TODO: determine component depth for YUV */
+ if (pix_format == DRM_FORMAT_P010)
+ pixel_depth = 30;
} else if (dcss_cs == DCSS_COLORSPACE_RGB) {
dcss_scaler_yuv_enable(dcss, ch_num, false);