diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-05-07 11:15:36 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 0c9c65fcd42abd5c961fc1ee6cf8c5f5351a8ad8 (patch) | |
| tree | 6fcb4132fcdcc5678f45554961d5e74797fa7140 /drivers/gpu/imx/dpu | |
| parent | 7ca3c70f94232ff619662828428f903dccfa0015 (diff) | |
MLK-18207 gpu: imx: framegen: Remove redundant pll and display clk rate get
We get pll and display clock rates twice in framegen_cfg_videomode().
This patch removes the redundant code so that the rates are got once.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'drivers/gpu/imx/dpu')
| -rw-r--r-- | drivers/gpu/imx/dpu/dpu-framegen.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c index 3e7655989ab6..50401fc297be 100644 --- a/drivers/gpu/imx/dpu/dpu-framegen.c +++ b/drivers/gpu/imx/dpu/dpu-framegen.c @@ -267,9 +267,6 @@ void framegen_cfg_videomode(struct dpu_framegen *fg, struct drm_display_mode *m) dpu_fg_write(fg, 0, FGCCR); mutex_unlock(&fg->mutex); - clk_get_rate(fg->clk_pll); - clk_get_rate(fg->clk_disp); - disp_clock_rate = m->clock * 1000; /* find an even divisor for PLL */ |