MLK-18576-3 drm/imx: ldb: Add dual channel mode support for i.MX8dx/dxp/qxp

i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode.  This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp.  Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

3 files changed, 14 insertions, 3 deletions

diff --git a/drivers/gpu/imx/dpu/dpu-common.c b/drivers/gpu/imx/dpu/dpu-common.c
index 8cd60b728178..2cf7a5055b9a 100644
--- a/drivers/gpu/imx/dpu/dpu-common.c
+++ b/drivers/gpu/imx/dpu/dpu-common.c
@@ -544,6 +544,7 @@ static const struct dpu_devtype dpu_type_v1 = {
 	.has_prefetch = false,
 	.has_prefetch_fixup = false,
 	.has_disp_sel_clk = false,
+	.has_dual_ldb = false,
 	.pixel_link_quirks = false,
 	.pixel_link_nhvsync = false,
 	.version = DPU_V1,
@@ -574,6 +575,7 @@ static const struct dpu_devtype dpu_type_v2_qm = {
 	.has_prefetch = true,
 	.has_prefetch_fixup = false,
 	.has_disp_sel_clk = true,
+	.has_dual_ldb = false,
 	.pixel_link_quirks = true,
 	.pixel_link_nhvsync = true,
 	.version = DPU_V2,
@@ -604,6 +606,7 @@ static const struct dpu_devtype dpu_type_v2_qxp = {
 	.has_prefetch = true,
 	.has_prefetch_fixup = true,
 	.has_disp_sel_clk = false,
+	.has_dual_ldb = true,
 	.pixel_link_quirks = true,
 	.pixel_link_nhvsync = true,
 	.version = DPU_V2,
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c
index f956da7fdca5..bb75bf8135b2 100644
--- a/drivers/gpu/imx/dpu/dpu-framegen.c
+++ b/drivers/gpu/imx/dpu/dpu-framegen.c
@@ -109,6 +109,7 @@ struct dpu_framegen {
 	int id;
 	bool inuse;
 	bool use_bypass_clk;
+	bool encoder_type_has_lvds;
 	struct dpu_soc *dpu;
 };
 
@@ -194,20 +195,24 @@ static void dpu_pixel_link_disable(int dpu_id, int stream_id)
 void framegen_enable(struct dpu_framegen *fg)
 {
 	struct dpu_soc *dpu = fg->dpu;
+	const struct dpu_devtype *devtype = dpu->devtype;
 
 	mutex_lock(&fg->mutex);
 	dpu_fg_write(fg, FGEN, FGENABLE);
 	mutex_unlock(&fg->mutex);
 
-	dpu_pixel_link_enable(dpu->id, fg->id);
+	if (!(devtype->has_dual_ldb && fg->encoder_type_has_lvds))
+		dpu_pixel_link_enable(dpu->id, fg->id);
 }
 EXPORT_SYMBOL_GPL(framegen_enable);
 
 void framegen_disable(struct dpu_framegen *fg)
 {
 	struct dpu_soc *dpu = fg->dpu;
+	const struct dpu_devtype *devtype = dpu->devtype;
 
-	dpu_pixel_link_disable(dpu->id, fg->id);
+	if (!(devtype->has_dual_ldb && fg->encoder_type_has_lvds))
+		dpu_pixel_link_disable(dpu->id, fg->id);
 
 	mutex_lock(&fg->mutex);
 	dpu_fg_write(fg, 0, FGENABLE);
@@ -225,7 +230,7 @@ EXPORT_SYMBOL_GPL(framegen_shdtokgen);
 
 void
 framegen_cfg_videomode(struct dpu_framegen *fg, struct drm_display_mode *m,
-		       bool encoder_type_has_tmds)
+		       bool encoder_type_has_tmds, bool encoder_type_has_lvds)
 {
 	const struct dpu_devtype *devtype = fg->dpu->devtype;
 	u32 hact, htotal, hsync, hsbp;
@@ -234,6 +239,8 @@ framegen_cfg_videomode(struct dpu_framegen *fg, struct drm_display_mode *m,
 	unsigned long disp_clock_rate, pll_clock_rate = 0;
 	int div = 0;
 
+	fg->encoder_type_has_lvds = encoder_type_has_lvds;
+
 	hact = m->crtc_hdisplay;
 	htotal = m->crtc_htotal;
 	hsync = m->crtc_hsync_end - m->crtc_hsync_start;
diff --git a/drivers/gpu/imx/dpu/dpu-prv.h b/drivers/gpu/imx/dpu/dpu-prv.h
index e03b962ce06a..ff1039005072 100644
--- a/drivers/gpu/imx/dpu/dpu-prv.h
+++ b/drivers/gpu/imx/dpu/dpu-prv.h
@@ -209,6 +209,7 @@ struct dpu_devtype {
 	bool has_prefetch;
 	bool has_prefetch_fixup;
 	bool has_disp_sel_clk;
+	bool has_dual_ldb;
 	bool pixel_link_quirks;
 	bool pixel_link_nhvsync;	/* HSYNC and VSYNC high active */
 	unsigned int version;