diff options
author | Yong Gan <yong.gan@nxp.com> | 2018-06-30 02:51:06 +0800 |
---|---|---|
committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
commit | a3b5e822333531c02fae46fe4e4629072ccad83e (patch) | |
tree | 6c4c704513b2a9620c3537111cee70513f388eb6 /drivers/gpu/imx | |
parent | ad5b24afad664f14018218967432db14eb9b9481 (diff) |
MGS-3560 [#imx-913] Enable DRM compression for mscale board
Refine the code for compressed format support.
Date: June 29, 2018
Signed-off-by: Yong Gan <yong.gan@nxp.com>
(cherry picked from commit 564b74a36e40cb340c697bce44e5523eed56c5c6)
Diffstat (limited to 'drivers/gpu/imx')
-rw-r--r-- | drivers/gpu/imx/dcss/dcss-dec400d.c | 116 |
1 files changed, 97 insertions, 19 deletions
diff --git a/drivers/gpu/imx/dcss/dcss-dec400d.c b/drivers/gpu/imx/dcss/dcss-dec400d.c index 639ed943eb18..9318e11f2595 100644 --- a/drivers/gpu/imx/dcss/dcss-dec400d.c +++ b/drivers/gpu/imx/dcss/dcss-dec400d.c @@ -18,23 +18,46 @@ #include <drm/drm_fourcc.h> #include <video/imx-dcss.h> +#include <video/viv-metadata.h> #include "dcss-prv.h" #define USE_CTXLD 1 /* DEC400D registers offsets */ -#define DEC400D_READCONFIG_BASE 0x800 -#define DEC400D_READCONFIG(i) (DEC400D_READCONFIG_BASE + ((i) << 2)) -#define COMPRESSION_ENABLE_BIT 0 -#define COMPRESSION_FORMAT_BIT 3 -#define COMPRESSION_ALIGN_MODE_BIT 16 -#define TILE_ALIGN_MODE_BIT 22 -#define TILE_MODE_BIT 25 -#define DEC400D_READBUFFERBASE0 0x900 -#define DEC400D_READCACHEBASE0 0x980 -#define DEC400D_CONTROL 0xB00 -#define DISABLE_COMPRESSION_BIT 1 -#define SHADOW_TRIGGER_BIT 29 +#define DEC400D_READCONFIG_BASE 0x800 +#define DEC400D_READCONFIG(i) (DEC400D_READCONFIG_BASE + ((i) << 2)) +#define DEC400D_READCONFIG_BASE 0x800 +#define DEC400D_READBUFFERBASE0 0x900 +#define DEC400D_READCACHEBASE0 0x980 +#define DEC400D_CONTROL 0xB00 +#define DEC400D_CLEAR 0xB80 + +#define COMPRESSION_ENABLE_BIT 0 +#define COMPRESSION_FORMAT_BIT 3 +#define COMPRESSION_ALIGN_MODE_BIT 16 +#define TILE_ALIGN_MODE_BIT 22 +#define TILE_MODE_BIT 25 +#define DISABLE_COMPRESSION_BIT 1 +#define SHADOW_TRIGGER_BIT 29 + +#define DEC400_CFMT_ARGB8 0x0 +#define DEC400_CFMT_XRGB8 0x1 +#define DEC400_CFMT_AYUV 0x2 +#define DEC400_CFMT_UYVY 0x3 +#define DEC400_CFMT_YUY2 0x4 +#define DEC400_CFMT_YUV_ONLY 0x5 +#define DEC400_CFMT_UV_MIX 0x6 +#define DEC400_CFMT_ARGB4 0x7 +#define DEC400_CFMT_XRGB4 0x8 +#define DEC400_CFMT_A1R5G5B5 0x9 +#define DEC400_CFMT_X1R5G5B5 0xA +#define DEC400_CFMT_R5G6B5 0xB +#define DEC400_CFMT_Z24S8 0xC +#define DEC400_CFMT_Z24 0xD +#define DEC400_CFMT_Z16 0xE +#define DEC400_CFMT_A2R10G10B10 0xF +#define DEC400_CFMT_BAYER 0x10 +#define DEC400_CFMT_SIGNED_BAYER 0x11 struct dcss_dec400d_priv { struct dcss_soc *dcss; @@ -118,7 +141,7 @@ void dcss_dec400d_bypass(struct dcss_soc *dcss) uint32_t control; struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv; - dcss_dec400d_read_config(dcss, 0, false); + dcss_dec400d_read_config(dcss, 0, false, 0); control = dcss_readl(dec400d->dec400d_reg + DEC400D_CONTROL); pr_debug("%s: dec400d control = %#x\n", __func__, control); @@ -169,8 +192,10 @@ EXPORT_SYMBOL(dcss_dec400d_addr_set); void dcss_dec400d_read_config(struct dcss_soc *dcss, uint32_t read_id, - bool compress_en) + bool compress_en, + uint32_t compress_format) { + uint32_t cformat = 0; uint32_t read_config = 0x0; struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv; @@ -183,17 +208,70 @@ void dcss_dec400d_read_config(struct dcss_soc *dcss, if (compress_en == false) goto config; - switch (dec400d->pixel_format) { - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XRGB8888: - read_config |= 0x0 << COMPRESSION_FORMAT_BIT; - break; + switch (compress_format) { + case _VIV_CFMT_ARGB8: + cformat = DEC400_CFMT_ARGB8; + break; + case _VIV_CFMT_XRGB8: + cformat = DEC400_CFMT_XRGB8; + break; + case _VIV_CFMT_AYUV: + cformat = DEC400_CFMT_AYUV; + break; + case _VIV_CFMT_UYVY: + cformat = DEC400_CFMT_UYVY; + break; + case _VIV_CFMT_YUY2: + cformat = DEC400_CFMT_YUY2; + break; + case _VIV_CFMT_YUV_ONLY: + cformat = DEC400_CFMT_YUV_ONLY; + break; + case _VIV_CFMT_UV_MIX: + cformat = DEC400_CFMT_UV_MIX; + break; + case _VIV_CFMT_ARGB4: + cformat = DEC400_CFMT_ARGB4; + break; + case _VIV_CFMT_XRGB4: + cformat = DEC400_CFMT_XRGB4; + break; + case _VIV_CFMT_A1R5G5B5: + cformat = DEC400_CFMT_A1R5G5B5; + break; + case _VIV_CFMT_X1R5G5B5: + cformat = DEC400_CFMT_X1R5G5B5; + break; + case _VIV_CFMT_R5G6B5: + cformat = DEC400_CFMT_R5G6B5; + break; + case _VIV_CFMT_Z24S8: + cformat = DEC400_CFMT_Z24S8; + break; + case _VIV_CFMT_Z24: + cformat = DEC400_CFMT_Z24; + break; + case _VIV_CFMT_Z16: + cformat = DEC400_CFMT_Z16; + break; + case _VIV_CFMT_A2R10G10B10: + cformat = DEC400_CFMT_A2R10G10B10; + break; + case _VIV_CFMT_BAYER: + cformat = DEC400_CFMT_BAYER; + break; + case _VIV_CFMT_SIGNED_BAYER: + cformat = DEC400_CFMT_SIGNED_BAYER; + break; default: /* TODO: not support yet */ WARN_ON(1); return; } + /* Dec compress format */ + read_config |= cformat << COMPRESSION_FORMAT_BIT; + /* ALIGN32_BYTE */ read_config |= 0x2 << COMPRESSION_ALIGN_MODE_BIT; |