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authorHiroshi DOYU <hdoyu@nvidia.com>2012-05-07 12:24:48 +0200
committerStephen Warren <swarren@nvidia.com>2012-05-08 13:30:49 -0600
commit87d0bab2cba3c31624b80cc68bcf5e29ef969458 (patch)
tree1bdf28fd56102096eba91cec450a5b2cced5ce75 /drivers/ide/slc90e66.c
parente816b57a337ea3b755de72bec38c10c864f23015 (diff)
ARM: tegra: Add Tegra AHB driver
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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