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authorHiroshi DOYU <hdoyu@nvidia.com>2012-05-10 10:45:32 +0300
committerJoerg Roedel <joerg.roedel@amd.com>2012-05-11 11:42:05 +0200
commit774dfc9bb7f2ab1950a790a8f13eca3d5c580033 (patch)
treec93680af050fcef7f5aff981ecfd3cf60abaf570 /drivers/iommu
parent7cffae421e3cd29410ef4d75f2244655fdde3b60 (diff)
iommu/tegra: gart: Fix register offset correctly
DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/tegra-gart.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 40533bba6254..0c0a37792218 100644
--- a/drivers/iommu/tegra-gart.c
+++ b/drivers/iommu/tegra-gart.c
@@ -36,9 +36,10 @@
/* bitmap of the page sizes currently supported */
#define GART_IOMMU_PGSIZES (SZ_4K)
-#define GART_CONFIG 0x24
-#define GART_ENTRY_ADDR 0x28
-#define GART_ENTRY_DATA 0x2c
+#define GART_REG_BASE 0x24
+#define GART_CONFIG (0x24 - GART_REG_BASE)
+#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
+#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
#define GART_PAGE_SHIFT 12